library verilog;
use verilog.vl_types.all;
entity MultSignPipe is
    generic(
        pmi_dataa_width : integer := 8;
        pmi_datab_width : integer := 8;
        pmi_pl          : integer := 1;
        module_type     : string  := "Mult"
    );
    port(
        PSA             : in     vl_logic_vector;
        PSB             : in     vl_logic_vector;
        PSClock         : in     vl_logic;
        PSClkEn         : in     vl_logic;
        PSAclr          : in     vl_logic;
        psproduct       : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_dataa_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_datab_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_pl : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end MultSignPipe;
